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Voltage scalable statistical gate delay models using neural networks

Das, BP and Amrutur, B and Jamadagni, HS (2007) Voltage scalable statistical gate delay models using neural networks. In: VLSI Design and Test 2007, Kolkota, Aug.2007 , Kolkota.

Full text not available from this repository.
Item Type: Conference Paper
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 13 Oct 2011 06:17
Last Modified: 13 Oct 2011 06:17
URI: http://eprints.iisc.ernet.in/id/eprint/41397

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