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A Low Power Frequency Multiplication Technique for Zigbee Transceiver

Pandey, Jagdish Nayayan and Kudva, Sudhir S and Amrutur, Bharadwaj (2007) A Low Power Frequency Multiplication Technique for Zigbee Transceiver. In: 20th International Conference on VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 6-10 Jan. 2007 , Bangalore.

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Abstract

A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a given output voltage swing using our technique. The advantages and disadvantages which determine the application areas of the technique are discussed. The issues related to design, layout and process variation are also addressed. Finally, a design is presented for operation in 2.405-2.485-GHz band of ZigBee receiver. SpectreRF simulations show 30% improvement in efficiency for our circuit with regard to conversion of DC bias current to output amplitude, against a LC-VCO. To establish the low-power credentials, we have compared our circuit with an existing technique; our circuit performs better with just 1/3 of total current from supply, and uses one inductor as against three in the latter case. A test chip was implemented in UMC 0.13-mum RF process with spiral on-chip inductors and MIM (metal-insulator-metal) capacitor option.

Item Type: Conference Paper
Additional Information: Copyright 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 14 Oct 2011 09:28
Last Modified: 14 Oct 2011 09:28
URI: http://eprints.iisc.ernet.in/id/eprint/41453

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