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Modified Stability Checking for On-Line Error Detection

Yada, Satish and Amrutur, Bharadwaj and Parekhji, Rubin A (2007) Modified Stability Checking for On-Line Error Detection. In: 20th International Conference on VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., Jan. 2007, Bangalore.

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Abstract

The paper propose a unified error detection technique, based on stability checking, for on-line detection of delay, crosstalk and transient faults in combinational circuits and SEUs in sequential elements. The proposed method, called modified stability checking (MSC), overcomes the limitations of the earlier stability checking methods. The paper also proposed a novel checker circuit to realize this scheme. The checker is self-checking for a wide set of realistic internal faults including transient faults. Extensive circuit simulations have been done to characterize the checker circuit. A prototype checker circuit for a 1mm2 standard cell array has been implemented in a 0.13mum process.

Item Type: Conference Paper
Additional Information: Copyright 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Concurrent testing;delay faults;crosstalk faults and transient faults;SEU testing;modified stability checking;self-checking circuits;on-line error detection
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 14 Oct 2011 09:33
Last Modified: 15 Jan 2013 05:36
URI: http://eprints.iisc.ernet.in/id/eprint/41454

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