A Scalable Low Power Store Queue For Large Instruction Window Superscalar processors

Vivekanandham, Rajesh and Govindarajan, R (2007) A Scalable Low Power Store Queue For Large Instruction Window Superscalar processors. In: Poster session at the Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT-2007), September 15--19, 2007, Brasov, Romania.

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Item Type:	Conference Paper
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation) Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited:	17 Oct 2011 05:25
Last Modified:	17 Oct 2011 05:25
URI:	http://eprints.iisc.ernet.in/id/eprint/41458

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