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Register Allocation and Optimal Spill code Scheduling in Software Pipelined Loops using 0-1 Integer Linear Programming Formulation

Nagarakatte, Santosh G and Govindarajan, R (2007) Register Allocation and Optimal Spill code Scheduling in Software Pipelined Loops using 0-1 Integer Linear Programming Formulation. In: CC'07 Proceedings of the 16th international conference on Compiler construction , Heidelberg.

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Official URL: http://dl.acm.org/citation.cfm?id=1759949

Abstract

In achieving higher instruction level parallelism, software pipelining increases the register pressure in the loop. The usefulness of the generated schedule may be restricted to cases where the register pressure is less than the available number of registers. Spill instructions need to be introduced otherwise. But scheduling these spill instructions in the compact schedule is a difficult task. Several heuristics have been proposed to schedule spill code. These heuristics may generate more spill code than necessary, and scheduling them may necessitate increasing the initiation interval. We model the problem of register allocation with spill code generation and scheduling in software pipelined loops as a 0-1 integer linear program. The formulation minimizes the increase in initiation interval (II) by optimally placing spill code and simultaneously minimizes the amount of spill code produced. To the best of our knowledge, this is the first integrated formulation for register allocation, optimal spill code generation and scheduling for software pipelined loops. The proposed formulation performs better than the existing heuristics by preventing an increase in II in 11.11% of the loops and generating 18.48% less spill code on average among the loops extracted from Perfect Club and SPEC benchmarks with a moderate increase in compilation time.

Item Type: Conference Paper
Additional Information: Copyright of this article belongs to Springer-Verlag Berlin.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 17 Oct 2011 05:15
Last Modified: 17 Oct 2011 05:15
URI: http://eprints.iisc.ernet.in/id/eprint/41461

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