Sen, Rathijit and Srikant, YN (2007) WCET Estimation for Executables in the Presence of Data Caches. In: EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software, October 2007, New York, NY.
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This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation, which is used for the dual purposes of tracking address computations and cache behavior. A simultaneous numeric and pointer analysis using an abstraction for discrete sets of values computes safe approximations of access addresses which are then used to predict cache behavior using Must Analysis. A heuristic is also proposed which generates likely worst case estimates. It can be used in soft real time systems and also for reasoning about the tightness of the safe estimate. The analysis methods can handle programs with non-affine access patterns, for which conventional Presburger Arithmetic formulations or Cache Miss Equations do not apply. The precision of the estimates is user-controlled and can be traded off against analysis time. Executables are analyzed directly, which, apart from enhancing precision, renders the method language independent.
|Item Type:||Conference Paper|
|Additional Information:||Copyright of this article belongs to ACM Press.|
|Department/Centre:||Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)|
|Date Deposited:||17 Oct 2011 08:57|
|Last Modified:||17 Oct 2011 08:57|
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