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Compiler-Directed Dynamic Voltage Scaling using Program Phases

Shyam, K and Govindarajan, R (2007) Compiler-Directed Dynamic Voltage Scaling using Program Phases. In: HiPC'07 Proceedings of the 14th international conference on High performance computing, Heidelberg.

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Official URL: http://dl.acm.org/citation.cfm?id=1782204

Abstract

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.

Item Type: Conference Paper
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 19 Oct 2011 07:06
Last Modified: 19 Oct 2011 07:06
URI: http://eprints.iisc.ernet.in/id/eprint/41519

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