Pai, Sreepathi and Govindarajan, R and Thazhuthaveetil, MJ (2007) Limits of Data Level Parallelism. In: 14th Annual IEEE International Conference on High Performance Computing (HiPC), Goa, December 2007 (poster presentation), December 2007, Goa.
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Abstract—A new breed of processors like the Cell Broadband Engine, the Imagine stream processor and the various GPU processors emphasize data-level parallelism (DLP) and threadlevel parallelism (TLP) as opposed to traditional instructionlevel parallelism (ILP). This allows them to achieve order-ofmagnitude improvements over conventional superscalar processors for many workloads. However, it is unclear as to how much parallelism of these types exists in current programs. Most earlier studies have largely concentrated on the amount of ILP in a program, without differentiating DLP or TLP. In this study, we investigate the extent of data-level parallelism available in programs in the MediaBench suite. By packing instructions in a SIMD fashion, we observe reductions of up to 91 % (84 % on average) in the number of dynamic instructions, indicating a very high degree of DLP in several applications. I.
|Item Type:||Conference Paper|
|Department/Centre:||Division of Information Sciences > Supercomputer Education & Research Centre|
|Date Deposited:||19 Oct 2011 06:54|
|Last Modified:||19 Oct 2011 06:54|
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