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VLSI Implementation of Spatial prediction Based Image Compression Scheme

Nandi, Anil V and Patnaik, LM and Banakar, RM (2007) VLSI Implementation of Spatial prediction Based Image Compression Scheme. In: First International Conference on Industrial and Information Systems, , 8-11 Aug. 2006 , Peradeniya .

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Abstract

We propose the design and implementation of hardware architecture for spatial prediction based image compression scheme, which consists of prediction phase and quantization phase. In prediction phase, the hierarchical tree structure obtained from the test image is used to predict every central pixel of an image by its four neighboring pixels. The prediction scheme generates an error image, to which the wavelet/sub-band coding algorithm can be applied to obtain efficient compression. The software model is tested for its performance in terms of entropy, standard deviation. The memory and silicon area constraints play a vital role in the realization of the hardware for hand-held devices. The hardware architecture is constructed for the proposed scheme, which involves the aspects of parallelism in instructions and data. The processor consists of pipelined functional units to obtain the maximum throughput and higher speed of operation. The hardware model is analyzed for performance in terms throughput, speed and power. The results of hardware model indicate that the proposed architecture is suitable for power constrained implementations with higher data rate

Item Type: Conference Paper
Additional Information: Copyright 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: spatial prediction;hierarchical tree;pipelining;parallelism.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Date Deposited: 10 Nov 2011 05:30
Last Modified: 10 Nov 2011 05:30
URI: http://eprints.iisc.ernet.in/id/eprint/41976

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