Das, Bishnu Prasad and Amrutur, Bharadwaj and Jamadagni, HS and Arvind, NV and Visvanathan, V (2011) Voltage and Temperature-Aware SSTA Using Neural Network Delay Model. In: IEEE Transactions on Semiconductor Manufacturing, 24 (4). pp. 533-544.
Voltage_and_Temperature.pdf - Published Version
Restricted to Registered users only
Download (617Kb) | Request a copy
With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4x less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.
|Item Type:||Journal Article|
|Additional Information:||Copyright 2011 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Keywords:||Linear SSTA;neural network;PVT-aware delay model;random local process variations;timing analysis in DVS|
|Department/Centre:||Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Division of Electrical Sciences > Electrical Communication Engineering
|Date Deposited:||23 Nov 2011 10:53|
|Last Modified:||23 Nov 2011 10:53|
Actions (login required)