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0.84 ps Resolution Clock Skew Measurement via Subsampling

Amrutur, Bharadwaj and Das, Pratap Kumar and Vasudevamurthy, Rajath (2011) 0.84 ps Resolution Clock Skew Measurement via Subsampling. In: IEEE Transactions on Very Large Scale Integration Systems, 19 (12). pp. 2267-2275.

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Abstract

An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes are sub-sampled with a near-frequency asynchronous sampling clock to result in beat signals which are themselves skewed in the same proportion but on a larger time scale. The beat signals are then suitably masked to extract only the skews of the rising edges of the clock signals. We propose a histogram of the arithmetic difference of the beat signals which decouples the relationship of clock jitter to the minimum measurable skew, and allows skews arbitrarily close to zero to be measured with a precision limited largely by measurement time, unlike the conventional XOR based histogram approach. We also analytically show that the proposed approach leads to an unbiased estimate of skew. The measured results from a 65 nm delay measurement front-end indicate that for an input skew range of +/- 1 fan-out-of-4 (FO4) delay, +/- 3 sigma resolution of 0.84 ps can be obtained with an integral error of 0.65 ps. We also experimentally demonstrate that a frequency modulation on a sampling clock maintains precision, indicating the robustness of the technique to jitter. We also show how FM modulation helps in restoring precision in case of rationally related clocks.

Item Type: Journal Article
Additional Information: Copyright 2011 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Arithmetic difference;asynchronous subsampling;clock skew measurement;frequency modulation;histogram analysis;time-to-digital converter
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 01 Dec 2011 10:33
Last Modified: 01 Dec 2011 10:33
URI: http://eprints.iisc.ernet.in/id/eprint/42398

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