Muralidharan, Girish and Bhat, Navakanta and Santhanam, Venugopal (2012) Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes. In: Nanoscale, 3 (11). pp. 4575-4579.
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We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices.
|Item Type:||Journal Article|
|Additional Information:||Copyright of this article belongs to Royal Society of Chemistry.|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering
Division of Mechanical Sciences > Chemical Engineering
Other Centres/Units/UG Programme > Centre for Nano Science and Engineering
|Date Deposited:||29 Nov 2011 09:24|
|Last Modified:||30 Nov 2011 07:24|
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