Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K and Larsson, Erik (2010) Energy-efficient redundant execution for chip multiprocessors. In: Proceedings of the 20th symposium on Great lakes symposium on VLSI (GLSVLSI '10), May 16-18, 2010, Brown University Campus, Providence, Rhode Island, USA.
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Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.
|Item Type:||Conference Proceedings|
|Additional Information:||Copyright belongs toACM New York, NY, USA|
|Department/Centre:||Division of Information Sciences > Supercomputer Education & Research Centre|
|Date Deposited:||14 Dec 2011 12:32|
|Last Modified:||14 Dec 2011 12:32|
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