Harish, BP and Bhat, Navakanta and Patil, Mahesh B (2006) Modeling of the Effects of Process Variations on Circuit Delay at 65nm. In: 2005 IEEE Conference on Electron Devices and Solid-State Circuits, 19-21 Dec. 2005, Bangalore, pp. 761-764.
Modeling_of_the.pdf - Published Version
Restricted to Registered users only
Download (1386Kb) | Request a copy
A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.
|Item Type:||Conference Paper|
|Additional Information:||Copyright 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Keywords:||process variations;mixed-mode simulations;Monte Carlo analysis;delay distribution;analytical modeling.|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering|
|Date Deposited:||27 Dec 2011 09:28|
|Last Modified:||27 Dec 2011 09:28|
Actions (login required)