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Improving Superscalar Instruction Dispatch And Issue By Exploiting Dynamic Code Sequences

Vajapeyam, Sriram and Mitra, Tulika (2002) Improving Superscalar Instruction Dispatch And Issue By Exploiting Dynamic Code Sequences. In: 1997. Conference Proceedings. The 24th Annual International Symposium on Computer Architecture, 2-4 Jun 1997.

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Abstract

Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, this increased fetch bandwidth cannot be exploited unless pipeline stages further downstream correspondingly improve. In particular,register renaming a large number of instructions per cycle is diDcult. A large instruction window, needed to receive multiple basic blocks per cycle, will slow down dependence resolution and instruction issue. This paper addresses these and related issues by proposing (i) partitioning of the instruction window into multiple blocks, each holding a dynamic code sequence; (ii) logical partitioning of the registerjle into a global file and several local jles, the latter holding registers local to a dynamic code sequence; (iii) the dynamic recording and reuse of register renaming information for registers local to a dynamic code sequence. Performance studies show these mechanisms improve performance over traditional superscalar processors by factors ranging from 1.5 to a little over 3 for the SPEC Integer programs. Next, it is observed that several of the loops in the benchmarks display vector-like behavior during execution, even if the static loop bodies are likely complex for compile-time vectorization. A dynamic loop vectorization mechanism that builds on top of the above mechanisms is briefly outlined. The mechanism vectorizes up to 60% of the dynamic instructions for some programs, albeit the average number of iterations per loop is quite small.

Item Type: Conference Paper
Additional Information: Copyright 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 27 Dec 2011 09:19
Last Modified: 27 Dec 2011 09:19
URI: http://eprints.iisc.ernet.in/id/eprint/42819

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