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A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

Vasudevamurthy, Rajath and Amrutur, Bharadwaj and Das, Pratap Kumar (2011) A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test. In: 2011 IEEE International Symposium on Circuits and Systems (ISCAS), 15-18 May 2011, Rio de Janeiro, Brazil.

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Abstract

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

Item Type: Conference Paper
Additional Information: Copyright 2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Quantization;current-starved;sub-sampling.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 23 Dec 2011 05:42
Last Modified: 23 Dec 2011 05:42
URI: http://eprints.iisc.ernet.in/id/eprint/42871

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