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An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology

Chaturvedi, Vikram and Amrutur, Bharadwaj (2011) An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology. In: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2011.

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Abstract

Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

Item Type: Conference Paper
Additional Information: Copyright 2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Alternating current (AC) coupling, bioamplifier;brain– machine interface (BMI);flicker;integrated;low noise amplifier (LNA);neural;noise;pseudoresistor;subthreshold.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 27 Dec 2011 08:26
Last Modified: 27 Dec 2011 08:26
URI: http://eprints.iisc.ernet.in/id/eprint/42901

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