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Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform

Biswas, Prasenjit and Alle, Mythri and Nandy, SK and Narayan, R and Varadarajan, Keshavan (2010) Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. In: 2010 International Conference on Embedded Computer Systems (SAMOS), 19-22 July 2010 , Samos.

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Abstract

In the world of high performance computing huge efforts have been put to accelerate Numerical Linear Algebra (NLA) kernels like QR Decomposition (QRD) with the added advantage of reconfigurability and scalability. While popular custom hardware solution in form of systolic arrays can deliver high performance, they are not scalable, and hence not commercially viable. In this paper, we show how systolic solutions of QRD can be realized efficiently on REDEFINE, a scalable runtime reconfigurable hardware platform. We propose various enhancements to REDEFINE to meet the custom need of accelerating NLA kernels. We further do the design space exploration of the proposed solution for any arbitrary application of size n × n. We determine the right size of the sub-array in accordance with the optimal pipeline depth of the core execution units and the number of such units to be used per sub-array.

Item Type: Conference Paper
Additional Information: Copyright 2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: QR Decomposition;Systolic arrays;Runtime Reconfigurable architectures;Honeycomb Network;Custom Mapping;Application Synthesis;Performance analysis
Department/Centre: Others
Date Deposited: 29 Dec 2011 08:57
Last Modified: 29 Dec 2011 08:57
URI: http://eprints.iisc.ernet.in/id/eprint/42944

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