Adapa, Anil Kumar and John, Vinod (2011) Digital Dead Time Logic and Protection Circuitry for PWM Voltage Source Converters. In: 5th National Power Electronics Conference 2011, 19-22 December 2011, Shibpur, Howrah, West Bengal, India.
npec_2011.pdf - Published Version
Power semiconductor devices have finite turn on and turn off delays that may not be perfectly matched. In a leg of a voltage source converter, the simultaneous turn on of one device and the turn off of the complementary device will cause a DC bus shoot through, if the turn off delay is larger than the turn on delay time. To avoid this situation it is common practice to blank the two complementary devices in a leg for a small duration of time while switching, which is called dead time. This paper proposes a logic circuit for digital implementation required to control the complementary devices of a leg independently and at the same time preventing cross conduction of devices in a leg, and while providing accurate and stable dead time. This implementation is based on the concept of finite state machines. This circuit can also block improper PWM pulses to semiconductor switches and filters small pulses notches below a threshold time width as the narrow pulses do not provide any significant contribution to average pole voltage, but leads to increased switching loss. This proposed dead time logic has been implemented in a CPLD and is implemented in a protection and delay card for 3- power converters.
|Item Type:||Conference Paper|
|Additional Information:||Copyright of this article belongs to National Power Electronics Conference.|
|Keywords:||Dead time;independent control;pulse fltering;fnite state machine|
|Department/Centre:||Division of Electrical Sciences > Electrical Engineering|
|Date Deposited:||23 Jan 2012 05:16|
|Last Modified:||24 Feb 2012 10:18|
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