Iyengar, Ramakrishna BS and Parthasarathy, K and Thukaram, D (1988) A multiprocessor architecture for high speed power system computations. In: Fifth National Power Systems Conference, 1988, CPRI, Bangalore.
Full text not available from this repository.| Item Type: | Conference Paper |
|---|---|
| Department/Centre: | Division of Electrical Sciences > Electrical Engineering |
| Date Deposited: | 10 May 2012 10:55 |
| Last Modified: | 10 May 2012 10:55 |
| URI: | http://eprints.iisc.ernet.in/id/eprint/44331 |
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