Mehta, Nandish and Amrutur, Bharadwaj (2012) Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 20 (5). pp. 892-901.
ieee_trans_vlsi_sys_20-5_892-901_2012.pdf - Accepted Version
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A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.
|Item Type:||Journal Article|
|Keywords:||CMOS; dynamic voltage and threshold scaling (DVTS); in-situ power monitor; leakage current control; low power; power optimum point; sleep transistor; variable body bias; variable supply voltage; V-DD - V-TH control|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering|
|Date Deposited:||08 Aug 2012 08:53|
|Last Modified:||08 Aug 2012 08:53|
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