ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Jandhyala, Srivatsava and Kashyap, Rutwick and Anghel, Costin and Mahapatra, Santanu (2012) A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry. In: IEEE Transactions on Electron Devices, 59 (4). pp. 1002-1007.

[img] PDF
ieee_tran_elet_dev_59-4_2012.pdf - Published Version
Restricted to Registered users only

Download (497Kb) | Request a copy
Official URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?...

Abstract

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Item Type: Journal Article
Additional Information: Copyright of this article is belongs to IEEE.
Keywords: Circuit simulation;compact modeling;double-gate (DG) MOSFET; terminal charge
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Date Deposited: 13 Aug 2012 10:30
Last Modified: 13 Aug 2012 10:31
URI: http://eprints.iisc.ernet.in/id/eprint/44485

Actions (login required)

View Item View Item