Medury, Aditya Sankar and Bhat, KN and Bhat, Navakanta (2012) Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor. In: Journal of Applied Physics, 112 (2).
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We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Î¦ c) saturates to Î¦ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Î¦ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. Â© 2012 American Institute of Physics.
|Item Type:||Journal Article|
|Additional Information:||Copyright for this article belongs to tehAmerican Institute of Physics|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering
Other Centres/Units/UG Programme > Centre for Nano Science and Engineering
|Date Deposited:||12 Sep 2012 06:58|
|Last Modified:||12 Sep 2012 06:58|
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