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A low-noise low-power noise-adaptive neural amplifier in 0.13um CMOS technology

Chaturvedi, Vikram and Amrutur, Bharadwaj S (2011) A low-noise low-power noise-adaptive neural amplifier in 0.13um CMOS technology. In: 2011 24th International Conference on VLSI Design (VLSI Design), 2-7 Jan. 2011, Chennai.

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Official URL: http://dx.doi.org/10.1109/VLSID.2011.41

Abstract

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and in elucidating human neurophysiology. The advent of multichannel microelectrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system is limited by background system noise which varies over time. We propose a neural amplifier in UMC 130 nm, 2P8M CMOS technology. It can be biased adaptively from 200 nA to 2 uA, modulating input referred noise from 9.92 uV to 3.9 uV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input DC offsets at electrode-electrolyte interface. The bandwidth of the amplifier can be tuned by the pseudo-resistor for selectively recording low field potentials (LFP) or extra cellular action potentials (EAP). The amplifier achieves a mid-band voltage gain of 37 dB and minimizes the attenuation of the signal from neuron to the gate of the input transistor. It is used in fully differential configuration to reject noise of bias circuitry and to achieve high PSRR.

Item Type: Conference Proceedings
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Additional Information: Copyright of this article belongs to IEEE.
Keywords: Neuron; Action Potentials; Analog Amplifier; Bio-Amplifier; Flicker Noise; Large Time Constant; Low Noise; Sub-Threshold Design
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 09 Apr 2013 10:03
Last Modified: 09 Apr 2013 10:03
URI: http://eprints.iisc.ernet.in/id/eprint/46209

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