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A Novel Design Method for SOGI-PLL for Minimum Settling Time and Low Unit Vector Distortion

Kulkarni, Abhijit and John, Vinod (2013) A Novel Design Method for SOGI-PLL for Minimum Settling Time and Low Unit Vector Distortion. In: 39th Annual Conference of the IEEE Industrial-Electronics-Society (IECON), NOV 10-14, 2013, Vienna, AUSTRIA, pp. 274-279.

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Official URL: http://dx.doi.org/10.1109/IECON.2013.6699148

Abstract

Phase-locked loops (PLLs) are necessary in grid connected systems to obtain information about the frequency, amplitude and phase of the grid voltage. In stationary reference frame control, the unit vectors of PLLs are used for reference generation. It is important that the PLL performance is not affected significantly when grid voltage undergoes amplitude and frequency variations. In this paper, a novel design for the popular single-phase PLL topology, namely the second-order generalized integrator (SOGI) based PLL is proposed which achieves minimum settling time during grid voltage amplitude and frequency variations. The proposed design achieves a settling time of less than 27.7 ms. This design also ensures that the unit vectors generated by this PLL have a steady state THD of less than 1% during frequency variations of the grid voltage. The design of the SOGI-PLL based on the theoretical analysis is validated by experimental results.

Item Type: Conference Paper
Additional Information: Copyright for this article belongs to the IEEE
Keywords: Phase locked loops; second order generalized integrator; harmonic distortion
Department/Centre: Division of Electrical Sciences > Electrical Engineering
Depositing User: Id for Latest eprints
Date Deposited: 04 Apr 2014 09:23
Last Modified: 04 Apr 2014 09:38
URI: http://eprints.iisc.ac.in/id/eprint/48784

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