Agarwal, Manvi and Nandy, SK and Eijndhoven, JV and Balakrishanan, S (2002) Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW Processors. In: 15th Symposium on Integrated Circuits and Systems Design, 9-14 September, Porto Alegre,Brazil, pp. 43-48.
VLIW processors are statically scheduled processors and their performance depends on the quality of schedules generated by the compiler's scheduler. We propose a multi-threaded architectural support for speculative trace scheduling in VLIW processors. In this multithreaded architecture the next most probable trace is speculatively executed, overlapping the stall cycles of the processor during cache misses and page faults. Switching between traces is achieved with the help of special hardware units viz. operation state buffers and trace buffers. We observe an 8.39% reduction in the overall misprediction penalty as compared to that incurred when the stall cycles due to cache misses alone are not overlapped.
|Item Type:||Conference Paper|
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|Department/Centre:||Division of Information Sciences > Supercomputer Education & Research Centre|
|Date Deposited:||27 Jan 2006|
|Last Modified:||19 Sep 2010 04:23|
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