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Power minimization using control generated clocks

Rao, Srikanth M and Nandy, SK (2000) Power minimization using control generated clocks. In: 37th Design Automation Conference, 5-9 June, 2000, Los Angeles, USA, 794 -799.

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Abstract

In this paper we describe an area efficient power minimization scheme “Control Generated Clocking I‘ that saves significant amounts of power in datapath registers and clock drivers of sequential circuits. Power savings are achieved by making simple changes to the state machines controlling the datapath. These changes enable the control signals from the state machines themselves to be used as clocks for the datapath registers. Use of these control generated clocks makes the static timing analysis of designs implementing this scheme simpler when compared to techniques such as clock gating. This scheme preserves the cycle boundaries on which registers load data, thereby allowing reuse of functional test cases developed for the original circuit. In this paper we also describe timing requirements of a design in which this scheme has been implemented, cost-benefit aspects of this scheme and an algorithm for the automatic synthesis of control generated clocks. Results from application of this technique on a complex design are then discussed.

Item Type: Conference Paper
Additional Information: ©ACM, 2000. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in Proceedings 2000: 37th Design Automation Conference.
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 05 Jul 2004
Last Modified: 19 Sep 2010 04:13
URI: http://eprints.iisc.ernet.in/id/eprint/528

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