# Implant Dose Sensitivity of $0.1\hspace{5mm}{\mu}m$ CMOS Inverter Delay

Srinivasaiah, HC and Bhat, Navakanta (2002) Implant Dose Sensitivity of $0.1\hspace{5mm}{\mu}m$ CMOS Inverter Delay. In: 7th Asia and South Pacific Design Automation Conference 15th International Conference on VLSI Design, 2002. ASP-DAC 2002, 7-11 January, Bangalore,India, 225 -230.

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## Abstract

The simulation experiment is performed to characterize the impact of process level fluctuations on the circuit performance variation for the $0.1\hspace{5mm}{\mu}m$ CMOS technology. The $0.1\hspace{5mm}{\mu}m$ NMOS and PMOS transistors are optimized using four different ion implantation steps namely super steep retrograde channel (SSRC) implant, deep s/d implant, shallow s/d extension implant and halo implant. We demonstrate that the fluctuations in the nominal values of these implant doses result in the significant variation in DC $(I_{off},\hspace{5mm}I_{on},\hspace{5mm}V_{t})$ and $AC\hspace{5mm}(C_{gg})$ parameters of the transistors. The DC and AC parameter variations of these devices in turn have their effect on the performance of the inverter circuit. In particular, the halo implant has the maximum impact resulting in ${\Delta}I_{off}\hspace{5mm}=\hspace{5mm}{122\%}\hspace{5mm}{(97.48\%)}$ and ${\Delta}I_{on}\hspace{5mm}=\hspace{5mm}{4.82\%}\hspace{5mm}{(5.29\%)}$ for NMOS (PMOS) transistor. The worst case delay variation is more than $\pm{10\%}$ for a $\pm{10\%}$ random variation in the implant dose parameters

Item Type: Conference Paper Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Division of Electrical Sciences > Electrical Communication Engineering 08 Feb 2006 19 Sep 2010 04:23 http://eprints.iisc.ernet.in/id/eprint/5297