Agrawal, Vikas and Pande, Anand and Mehendale, Mahesh M (2001) High Level Synthesis of Multi-precision Data Flow Graphs. In: Fourteenth International Conference on VLSI Design, 2001, 3-7 January, Bangalore,India, pp. 411-416.
A number of DSP algorithms involve linear transforms employing weighted sum computations, where the weights are fixed at design time. Add-shift implementation of such a computation results in a data flow graph that has multiple precision variables and functional units. We explore the potential of precision sensitive approach for the high level synthesis of such multi-precision DFGs. We focus on fixed latency implementation of these DFGs. We present register allocation, functional unit binding and scheduling algorithms to exploit the multi-precision nature of such DFGs for area efficient implementation. The proposed approach is fairly generic and could be applied to multi-precision DFGs involving any type of functional units. Significant improvements of upto $27\%$ have been obtained over the conventional high-level synthesis approach.
|Item Type:||Conference Paper|
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|Department/Centre:||Division of Information Sciences > Supercomputer Education & Research Centre|
|Date Deposited:||15 Feb 2006|
|Last Modified:||19 Sep 2010 04:23|
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