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A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan

Ahlawat, Satyadev and Tudu, Jaynarayan and Matrosova, Anzhela and Singh, Virendra (2015) A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. In: 24th IEEE Asian Test Symposium, NOV 22-25, 2015, Mumbai, INDIA, pp. 25-30.

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Official URL: http://dx.doi.org/10.1109/ATS.2015.12

Abstract

The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational depth decreases, the performance degradation caused by scan multiplexer delay become more critical. Elimination of the scan multiplexer delay off the functional path has become crucial in maintaining the circuit performance. In this work we propose a new transistor level scan cell design to eliminate the scan multiplexer off the functional path. The proposed scan cell uses separate master latch for functional and test mode where as the slave latch is same in both the modes. Our proposed scan flip-flop fully comply with the conventional test flow. Post layout experimental results justify the effectiveness of the proposed scan cell design in eliminating the performance penalty of scan, and thus in improving the timing performance of integrated circuits.

Item Type: Conference Paper
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Additional Information: Copy right for this article belongs to the IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Date Deposited: 07 Dec 2016 04:35
Last Modified: 07 Dec 2016 04:35
URI: http://eprints.iisc.ernet.in/id/eprint/55448

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