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A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA

Datta, Saugata and Varghese, Kuruvilla and Srinivasa, Shayan Garani (2016) A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. In: 29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID), JAN 04-08, 2016, Kolkata, INDIA, pp. 439-444.

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Official URL: http://dx.doi.org/10.1109/VLSID.2016.92

Abstract

Soft output Viterbi detectors ( SOVA) are universally used in all communication receivers within the digital back-end circuitry for mitigating intersymbol interference. Current implementations of the SOVA detector are based on uniform quantization using register exchange logic or with a traceback approach. In this paper, we investigate the design architecture and performance analysis of a SOVA detector based on non-uniform quantization. The proposed detector was synthesized and place and routed using Xilinx tool chain and implemented on Kintex-7 XC7K325T field programmable gate array ( FPGA) kit. Implementation results in FPGA shows that our proposed architecture results in a 10.25% reduction in the total number of slice registers, 8.35% reduction in the number of slice look-up table ( LUT) and reduction in the critical path delay leading to an estimated throughput of 2.15 Gbps with no performance loss compared to the uniform quantization scheme.

Item Type: Conference Proceedings
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Additional Information: Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 07 Dec 2016 06:02
Last Modified: 07 Dec 2016 06:02
URI: http://eprints.iisc.ernet.in/id/eprint/55563

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