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Design of a fast response time single-phase PLL with dc offset rejection capability

Kulkarni, Abhijit and John, Vinod (2017) Design of a fast response time single-phase PLL with dc offset rejection capability. In: ELECTRIC POWER SYSTEMS RESEARCH, 145 . pp. 35-43.

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Official URL: http://dx.doi.org/10.1016/j.epsr.2016.12.023

Abstract

Second-order generalized integrator (SOGI) based phase-locked loops (PLLs) are commonly used for grid voltage synchronization in single-phase grid-connected power converters. SOGI-PLLs are attractive because of their simple structure that makes them suitable for implementation even in low-end digital controllers. In this paper, an SOGI based fixed-parameter PLL structure with full dc offset rejection capability is presented. This PLL uses two cascaded SOGI structures and it is termed as cascaded generalized integrator PLL (CGI-PLL). A systematic design procedure is proposed for the CGI-PLL that minimizes the response time and unit vector harmonic distortion. This design achieves minimum settling time for any given worst-case frequency deviation in the grid voltage and ensures that the unit vector THD is less than 1%. The PLL designed using the proposed method has good harmonic attenuation capability. The steady-state and transient response of this PLL have been validated experimentally and are found to agree with the theoretical analysis. (C) 2016 Elsevier B.V. All rights reserved.

Item Type: Journal Article
Additional Information: Copy right for this article belongs to the ELSEVIER SCIENCE SA, PO BOX 564, 1001 LAUSANNE, SWITZERLAND
Department/Centre: Division of Electrical Sciences > Electrical Engineering
Depositing User: Id for Latest eprints
Date Deposited: 26 Apr 2017 07:23
Last Modified: 26 Apr 2017 07:23
URI: http://eprints.iisc.ac.in/id/eprint/56638

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