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A Self-Biased High Performance Folded Cascode CMOS Op-Amp

Mandal, Pradip and Visvanathan, V (1997) A Self-Biased High Performance Folded Cascode CMOS Op-Amp. In: Tenth International Conference on VLSI Design, 1997, 4-7 January, Hyderabad,India, 429 -434.

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Abstract

Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise and cross-talk and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no baas voltages other than the two supply rails. The resulting self-biased op-amps are free from the above mentioned drawbacks and exhibit the same performance as existing folded casode op-amps, except for a small reduction in slew rate. This is achieved by following transistor sizing constraints derived through detailed circuit analysis. The technique is applied to an existing high performance op-amp. Simulation results show that the high performance is maintained while nine bias voltages are eliminated.

Item Type: Conference Paper
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 25 Aug 2008
Last Modified: 19 Sep 2010 04:25
URI: http://eprints.iisc.ernet.in/id/eprint/6396

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