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Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs

Jacob, James and Sivakumar, PS and Agrawal, Vishwani D (1997) Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. In: Tenth International Conference on VLSI Design, 1997, 4-7 January, Hyderabad,India, 514 -515.

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Abstract

An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation f or adder and comparator circuits. For n bat adder circuits, the size of P L A for transformed functions is $O(n^2)$. In comparison, when the complete truth-table of an adder is minimized, the PLA size will be $0(2^{n+2})$. Similarly, for an n bit comparator, the size of the PLA is reduced from $0(2^{n+1})$ to O(n). These implementations require additional transform logic of complexity O(n), consisting of exclusive-OR gates.

Item Type: Conference Paper
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 25 Aug 2008
Last Modified: 19 Sep 2010 04:25
URI: http://eprints.iisc.ernet.in/id/eprint/6397

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