Ramanathan, S and Visvanathan, V (1996) A Systolic Architecture for LMS Adaptive Filtering with Minimal Adaptation Delay. In: Ninth International Conference on VLSI Design, 1996, 3-6 January, Bangalore,India, pp. 286-289.
Existing systolic architectures for the LMS algorithm with delayed coefficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents a systolic architecture with minimal adaptation delay and input/output latency, thereby improving the convergence behaviour to near that of the original LMS algorithm. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the delayed LMS algorithm. With the use of carry-save arithmetic, the systolic folded pipelined architecture can support very high sampling rates, limited only by the delay of a full adder.
|Item Type:||Conference Paper|
|Additional Information:||Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Information Sciences > Supercomputer Education & Research Centre|
|Date Deposited:||22 Aug 2008|
|Last Modified:||19 Sep 2010 04:26|
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