Somasekhar, Dinesh and Visvanathan, V (1993) A 230-MHz Half-Bit Level Pipelined Multiplier Using True Single-Phase Clocking. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1 (4). pp. 415-422.
An 8-bit×8-bit signed two's complement pipelined multiplier megacell implemented in 1.6-\mu m single-poly, double-metal N-well CMOS is described. It is capable of throughputs of 230,000,000 multiplications/s at a clock frequency of 230 MHz, with a latency of 12 clock cycles. A half-bit level pipelined architecture, and the use of true single-phase clocked circuitry are the key features of this design. Simulation studies indicate that the multiplier dissipates 540 mW at 230 MHz. The multiplier cell has 5176 transistors, with dimensions of 1.5 mm×1.4 mm. This multiplier satisfies the need for very high-throughput multiplier cores required in DSP architectures.
|Item Type:||Journal Article|
|Additional Information:||Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Information Sciences > Supercomputer Education & Research Centre
Division of Electrical Sciences > Electrical Communication Engineering
|Date Deposited:||22 Aug 2008|
|Last Modified:||19 Sep 2010 04:26|
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