Ghosh, Debabrata and Nandy, SK and Parthasarathy, K and Visvanathan, V (1993) NPCPL : Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. In: The Sixth International Conference on VLSI Design,1993, 3-6 January, Bombay,India, pp. 341-346.
High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both of t h e m simultaneously. We propose a Normal Process Complementary Pass Transistor Logic (NPCPL) which can be used as a universal logic to provide finest grain pipelining without affecting overall latency o r increasing the area. It does n o t require any special process steps and hence, can be Tealised in a normal process technology as against the CPL proposed by Yano et al  which uses threshold voltage adjustment of selected devices. The design procedure is described for (a)low latency, (b)high throughput and (c)low area requirements. In addition to the various advantages, it is envisioned that NPCPL designs can also be used to build ultra-high speed pipelined system without pipelining latches, viz., wave pipelined digital systems, where the throughput achievable is beyond that permitted by the delay of a pipeline stage.
|Item Type:||Conference Paper|
|Additional Information:||Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Electrical Sciences > Electrical Engineering
Division of Electrical Sciences > Electrical Communication Engineering
|Date Deposited:||25 Aug 2008|
|Last Modified:||19 Sep 2010 04:26|
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