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An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters

Visvanathan, V and Mohanty, Nibedita and Ramanathan, S (1993) An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. In: Sixth International Conference on VLSI Design,1993, 3-6 January, Bombay,India, pp. 166-171.

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Abstract

An area-effcient systolic architecture for realtime, programmable-coefficient finite impulse response (FIR) filters is presented. A technique called pipelined clustering is introduced to derive the architecture in which a number of filter tap computations are multiplexed in an appropriately pipelined processor. This multiplezing is made possible by the fact that the processor is clocked at the highest possible frequency under the given. technology and design constraints. Reduction in hardware proportional to the ratio of data arrival period and clock period is achieved. The proposed systolic architecture is 100% efficient and has the same throughput and latency and approximately the same power dissipation as an unclustered array. The architecture is completely specified, including a description, of the multip1exers and synchronisation delays that are required.

Item Type: Conference Paper
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 25 Aug 2008
Last Modified: 19 Sep 2010 04:26
URI: http://eprints.iisc.ernet.in/id/eprint/6808

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