Somasekhar, Dinesh and Visvanathan, V (1993) A 23Q MHz Half Bit Level Pipelined Multiplier using True Single Phase Clocking. In: Sixth International Conference on VLSI Design, 1993, 3-6 January, Bombay,India, 347 -350.
An 8 bit by 8 bit signed two's complement pipelined multiplier in 1.6$_\mu$m N well CMOS, capable of throughputs o f 230 million multiplications per second, is described. A half bit level pipelined architecture, and the use o f true single phase clocked circuitry, are the key features of this design. Simulation studies indicate that the multiplier dissipates 540mW at 230MHz. The chip complexity i s 5176 transistors, and the area is 1.5mmx 1.4mm.
|Item Type:||Conference Paper|
|Additional Information:||Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering|
|Date Deposited:||28 Nov 2007|
|Last Modified:||19 Sep 2010 04:27|
Actions (login required)