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Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree Structures

Srinivas, Sampalli and Biswas, Nripendra N (1992) Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree Structures. In: IEEE Transactions on Computers, 41 (11). pp. 1465-1478.

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Abstract

This paper presents a generalized architecture for reconfigurable m -ary tree structures, where m is any integer > 1. The approach is based on a generalized multistage interconnection network (MIN), which is a generalization of the augmented shuffle-exchange MIN introduce by the authors in [1] for obtaining reconfigurable binary tree structures. The generalized architecture with $m^k$ processing elements or nodes (where k is any integer > 1)is implemented with a k-stage MIN. A single control code issued to the MIN establishes a distinct m-ary tree configuration among the nodes. The archiecture can assume $m.2^{[log_2m](k-1)}$ distinct m-ary tree configration, one for each value of the control code.The favorable features of the architecture include fast reconfiguration, simplified hardware in the nodes and the MIN, and simple routing control. The generation of reconfigurable m-ary tree structures is based on a generalized reconfiguration equation. Analysis of this equation is carried out to prove the reconfigurability of the architecture. The results of the analysis are utilized to provide a procedure to synthesize the m-ary tree configuration that is generated for any given control code. Furthermore, considerations for implementing the switching elements of the MIN are discussed.

Item Type: Journal Article
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Intra-topology reconfiguration;m-ary shuffle;m-ary tree structures;Multistage interconnection networks;Reconfigurable parallel architecture;Switching elements;Switching theory
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 27 May 2006
Last Modified: 19 Sep 2010 04:27
URI: http://eprints.iisc.ernet.in/id/eprint/6824

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