Rathna, GN and Nandy, SK and Parthasarathy, K (1994) A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. In: Seventh International Conference on VLSI Design, 1994, 5-8 January, Kolkata, pp. 225-228.
In this paper, we propose an architecture synthesis methodology to realize cascaded infinite impulse response (IIR) filter in table look up (TLU) field programmable gate arrays (FPGA). The synthesis procedure involves a systematic transformation of the dependance graph (DG) corresponding to the cascaded IIR filler to a pipelined fixed full size array (PFFSA). We offer an implementation of a cascaded 8th order IIR filters on Xilinx XC3090 FPGA devices.
|Item Type:||Conference Paper|
|Additional Information:||Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Information Sciences > Supercomputer Education & Research Centre
Division of Electrical Sciences > Electrical Engineering
|Date Deposited:||25 Aug 2008|
|Last Modified:||19 Sep 2010 04:27|
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