Maitra, K and Bhat, N (2003) Polyreoxidation process step for suppressing edge direct tunneling through ultrathin gate oxides in NMOSFETs. In: Solid-State Electronics, 47 (1). pp. 15-17.
Restricted to Registered users only
Download (113Kb) | Request a copy
In this work, we identify polyreoxidation as a process step for selectively thickening the gate oxide at the edges (in the gate overlap region), and hence for suppressing the edge component of direct tunneling through ultrathin gate oxides in NMOSFETs. It is shown that by varying the different polyreoxidation parameters viz: temperature and polyreoxidation time it is possible to achieve different levels of gate oxide edge thickening. This essentially implies that a desired level of gate leakage current may be maintained without modifying the gate oxidation process significantly.
|Item Type:||Journal Article|
|Additional Information:||Copyright of this article belongs to Elsevier.|
|Keywords:||Band-to-band tunneling;Direct tunneling;dge direct tunneling;Gate induced drain Leakage;Overlap;Polyreoxidation;Source drain extension|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering|
|Date Deposited:||31 May 2006|
|Last Modified:||19 Sep 2010 04:28|
Actions (login required)