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T-Algorithm-Based Logic Simulation on Distributed Systems

Sundaram, S and Patnaik, LM (1992) T-Algorithm-Based Logic Simulation on Distributed Systems. In: Second Great Lakes Symposium on VLSI, 1992, 28-29 February, Kalamazoo,MI, pp. 191-195.

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Abstract

Increase in the complexity of VLSI digital circuit it sign demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic simulataon algorithms is by exploiting the inherent parallelism an the sequentaal versaon. In this paper, we explore the possibility of mapping a T-algoriihm based logac samulataon algorithm onto a cluster of workstation interconnected by an ethernet. The set of gates at a particular level as partitioned by the hiaster Task (running on the host processor) among the Slave Tasks (running on the other processors). Each Slave Task evaluates the set of gates assigned to at, for the complete simulation period independent of other slave tasks and communicates the evaluated outputs to the Master Task. After receiving the evaluated output from all the Slaves, the Master Task partitions the gates at the nexy level and communicates this new set of gates to the slave tasks. The above process as repeated for all the levels an the circuit. The detazls of the partitioning scheme and its performance are also discussed. We have implemented this dastrabuted logic simulation algorathm on a set of 8 VAX stations using the communication primitives (send and 'receave'provided as system calls. The paper concludes wzth a tabulated results on the speedup figures obtained on the ISCAS [8] bench in ark circuiis.

Item Type: Conference Paper
Additional Information: Copyright 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 01 Jun 2006
Last Modified: 19 Sep 2010 04:28
URI: http://eprints.iisc.ernet.in/id/eprint/7260

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