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Reconfigurable Filter Coprocessor Architecture for DSP Applications

Ramanathan, S and Nandy, SK and Visvanathan, V (2000) Reconfigurable Filter Coprocessor Architecture for DSP Applications. In: The Journal of VLSI Signal Processing, 26 (3). pp. 333-359.

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Abstract

Digital signal processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational complexity. Usually these cores are ASICs that cannot be easily retargeted for other similar applications that share certain commonalities. This stretches the design cycle that affects time-to-market constraints. We present a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications. The coprocessor architecture, apart from having the performance and power advantage of its ASIC counterpart, can be reconfigured to support a wide variety of filtering computations. Since filtering computations abound in DSP applications, the implementation of this coprocessor architecture can serve as an important embedded hardware IP

Item Type: Journal Article
Additional Information: Copyright of this article belongs to Springer.
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 10 Jul 2006
Last Modified: 27 Aug 2008 12:14
URI: http://eprints.iisc.ernet.in/id/eprint/7845

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