ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Line coverage of path delay faults

Majhi, Ananta K and Agrawal, Vishwani D and Jacob, James and Patnaik, Lalit M (2000) Line coverage of path delay faults. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8 (5). pp. 610-614.

[img] PDF
Line_Coverage_of_Path_Delay_Faults.pdf
Restricted to Registered users only

Download (114Kb) | Request a copy

Abstract

We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition,but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus,the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits.

Item Type: Journal Article
Additional Information: Copyright of this article belongs to IEEE.
Keywords: Delay faults;Fault coverage;Fault modeling;Test generation; VLSI testing.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Date Deposited: 25 Aug 2008
Last Modified: 19 Sep 2010 04:30
URI: http://eprints.iisc.ernet.in/id/eprint/8164

Actions (login required)

View Item View Item