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VLSI architecture for the Winograd Fourier Transform algorithm

Gopal, B and Manohar, S (1994) VLSI architecture for the Winograd Fourier Transform algorithm. In: Microprocessing & Microprogramming, 40 (9). pp. 605-616.

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Abstract

A simple systolic architecture for the computation of the DFT using the Winograd Fourier Transform algorithm is presented. The architecture is shown to be problem-size independent and to satisfy the limited bandwidth constraint. By satisfying the above constraints, it is then shown to be naturally scalable within the limits allowed by the Winograd algorithm. The proposed architecture is compared with existing VLSI solutions using Winograd's technique. Lastly, the feasibility of deriving and using Winograd type algorithms for larger primes and prime-powers is studied.

Item Type: Journal Article
Additional Information: Copyright of this article belongs to Elsevier.
Keywords: Discrete Fourier transform;Special-purpose VLSI architecture;Winograd algorithm;Systolic architecture
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Date Deposited: 16 Oct 2006
Last Modified: 19 Sep 2010 04:30
URI: http://eprints.iisc.ernet.in/id/eprint/8237

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