Suresh, PR and Ramkumar, K and Satyam, M (1991) Capacitance-voltage characteristics of grain boundaries in cast polycrystalline silicon. In: Journal of Applied Physics, 69 (12). pp. 8217-8221.
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This paper reports capacitance-voltage measurements of grain boundaries made on cast polycrystalline silicon wafers. It has been observed that unlike the case of symmetric grain boundaries, the capacitance-voltage characteristics measured at high frequency, depend upon the polarity of the applied dc voltage. This deviation has been attributed to the difference in conductivities in the grains forming the grain boundary. Based on this, capacitance-voltage characteristics of grain boundaries have been calculated. Carrier trapping and emission by the grain boundary states have been considered to calculate the change in the filled trap state density due to the applied bias. A monoenergetic trap level has been assumed. The computed capacitance-voltage curves justify the observed variations.
|Item Type:||Journal Article|
|Additional Information:||Copyright of this article belongs to American Institute of Physics.|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering|
|Date Deposited:||15 Sep 2006|
|Last Modified:||19 Sep 2010 04:31|
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