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Number of items: 6.

Conference Paper

Harish, BP and Bhat, Navakanta and Patil, Mahesh B (2007) Process variability-aware statistical hybrid modeling of dynamic power dissipation in 65 nm CMOS designs. In: International Conference on Computing - Theory and Applications (ICCTA 2007), MAR 05-07, 2007, Calcutta.

Harish, BP and Bhat, Navakanta and Patil, Mahesh B (2006) Modeling of the Effects of Process Variations on Circuit Delay at 65nm. In: 2005 IEEE Conference on Electron Devices and Solid-State Circuits, 19-21 Dec. 2005, Bangalore, pp. 761-764.

Harish, BP and Bhat, Navakanta (2006) Resistive Modeling of Estimation of Static Leakage Power in Nanoscale CMOS. In: IMAPS India National Conference, , December 2006, Hyderabad.

Journal Article

Harish, BP and Bhat, Navakanta (2012) Performance and variability trade-off with gate-to-source/drain overlap length. In: IETE Journal of Research, 58 (2). pp. 130-137.

Harish, BP and Bhat, Navakanta and Patil, Mahesh B (2007) On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. In: IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems, 26 (3). pp. 606-614.

Harish, BP and Bhat, Navakanta and Patil, Mahesh B (2006) Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes. In: Solid-State Electronics, 50 (7-8). pp. 1252-1260.

This list was generated on Wed Dec 17 22:33:45 2014 IST.