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Conference Proceedings

Gulur, Nagendra and Govindarajan, R and Mehendale, Mahesh (2016) MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. In: International Symposium on Memory Systems (MEMSYS), OCT 03-06, 2016, Washington, DC, pp. 350-361.

Gulur, Nagendra and Mehendale, Mahesh and Manikantan, R and Govindarajan, R (2014) Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. In: 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), DEC 13-17, 2014, Cambridge, ENGLAND, pp. 38-50.

Conference Paper

Gulur, Nagendra Dwarakanath and Manikantan, R and Mehendale, Mahesh and Govindarajan, R (2012) Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. In: ICS '12 Proceedings of the 26th ACM International Conference on Supercomputing, 2012, New York, NY, USA.

Menon, Amitabh and Nandy, SK and Mehendale, Mahesh (2003) Multivoltage Scheduling with Voltage-Partitioned Variable Storage. In: 2003 International Symposium on Low Power Electronics and Design, August 25 - 27, 2003, Seoul, Korea, pp. 298-301.

Mahesh, MN and Mehendale, Mahesh (1999) Improving Area Efficiency of Residue Number System Based Implementation of DSP Algorithms. In: Twelfth International Conference On VLSI Design, 1999, 7-10 January, Goa, India, pp. 340-345.

Mahesh, MN and Mehendale, Mahesh (1999) Improving Performance of High Precision Signal Processing Algorithms on Programmable DSPs. In: 1999 IEEE International Symposium on Circuits and Systems. ISCAS '99, 30 May-2 June, Orlando,Florida, Vol.3, 488-491.

Journal Article

Chandar, Subash and Mehendale, Mahesh and Govindarajan, R (2006) Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. In: Journal of VLSI Signal Processing Systems, 44 (3). pp. 245-267.

This list was generated on Sun Apr 5 23:06:45 2020 IST.