ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Browse by Author

Up a level
Export as [feed] Atom [feed] RSS 1.0 [feed] RSS 2.0
Group by: Item Type | No Grouping
Number of items: 2.

Conference Paper

Somasekhar, Dinesh and Visvanathan, V (1993) A 23Q MHz Half Bit Level Pipelined Multiplier using True Single Phase Clocking. In: Sixth International Conference on VLSI Design, 1993, 3-6 January, Bombay,India, 347 -350.

Journal Article

Somasekhar, Dinesh and Visvanathan, V (1993) A 230-MHz Half-Bit Level Pipelined Multiplier Using True Single-Phase Clocking. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1 (4). pp. 415-422.

This list was generated on Tue Sep 24 01:17:02 2019 IST.